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AS3691
Datasheet
Then calculate the maximum power dissipation inside the AS3691. The worst case is maximum voltage supply
(13V + 10%) together with LEDs with minimum forward voltage Uf min :
For these conditions the maximum voltage on any current source (CURR1 to CURR4) is
VCURR MAX = ( 1 + VDD TOL ) VDD ? n U f min
Not using automatic supply regulation
In our example 14.3V – 9.6V = 4.7V. The maximum power dissipation inside the AS3691 is now (assuming 4
identical strings)
P MAX = 4 VCURR MAX ICURR
In our example 1.88W. As
T MAX =
PT ? P MAX
P DERATE
+ 50 o C
For PT and P DERATE see Absolute
Maximum Ratings
the system can be operated safely up to an ambient temperature of 55 ° C assuming worst case power supplies
and worst case leds. Please note: If the internal junction temperature of the AS3691 rises too high, the AS3691
will switch off the current sources for protection (it will never damage the AS3691).
9.1.1 Using Automatic Supply Regulation
For the identical system using the automatic supply regulation, the supply is regulated to minimize the power
dissipation of the system. Therefore the tolerance of the VDD supply and also the variation in forward voltages of
the LEDs can be ignored (only the difference in one lot of leds is still important, as the four strings are connected
in parallel to the power supply). Assume a difference of Δ Uf = 0.2V of forward voltage of the leds in one lot, then
calculate the maximum voltage on the current source of the AS3691 (CURR1 to CURR4) with
Using automatic supply regulation
VCURR MAX = n Δ U f + V C
Δ Uf variation of LED forward voltage
in one lot (for one application)
V C is internal set voltage (1.0V)
to be 1.6V. Using the identical formulas as above, P MAX now is 0.64W and T MAX is 110 ° C.
Therefore using automatic supply regulation, the ambient temperature can be up to 110 ° C under identical
conditions.
9.2 Layout Recommendations
See austriamicrosystems ‘AN3691_TECH_Module Description’ as a layout example for the AS3691.
Layout Checklist
1. Use the bottom layer as ground plane and minimize the number and the length of connections within
this layer
2. Do as many vias as possible on the exposed pad (for thermal performance) to the ground plane
3. Connect RFBx and RESx together at the current set resistor Rix (see above recommended layout)
4. The ground connections of the current set resistors should be as close to the AS3691 as possible
5. The ground connection of the capacitor Cvdd should be as close as possible to the AS3691
6. Minimize Area build by ‘Csup VSS connection – Csup Supply Connection – LEDs – CURRx – Csup
VSS connection’ (to minimize inductance in this path)
www.austriamicrosystems.com (ptr)
Revision 2.3
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